1. Field of the Invention
The present invention relates to a reference voltage circuit, and particularly to a reference voltage circuit having a CMOS current mirror circuit therein.
2. Description of the Related Art
Conventionally, a reference voltage circuit of this type has been widely adopted within a CMOS semiconductor integrated circuit to produce potentials of different magnitude based on a power supply voltage. The reference voltage circuit being widely adopted includes a CMOS current mirror circuit. That is, the reference voltage circuit is configured to have a PMOS current mirror circuit provided therein and supply bias currents (constant currents) to a load circuit consisting of NMOS transistors, resistors and a diode from the current mirror circuit, in order to output a reference voltage through an output terminal.
FIG. 1 is a circuit diagram illustrating an example of the conventional reference voltage circuit. The conventional reference voltage is a most popular circuit comprising two NMOS transistors N1, N2, a source resistor R2, three PMOS transistors P1, P2, P3, an output resistor R3, and a diode D3.
When assuming a transistor has a channel width W and a channel length L, the current capacity of the MOS transistor is generally related to a ratio of the channel width to the channel length (W/L) of the transistor. The two NMOS transistors N1, N2 are provided such that the NMOS transistor N2 is scaled by a factor of m relative to the NMOS transistor N1. In this case, the scaling factor m is determined by the ratio of the W/L of the NMOS transistor N2 to the W/L of the NMOS transistor N1. Furthermore, the NMOS transistor N1, N2 have drains connected respectively to two nodes 1, 2 and gates commonly connected to the node 1, forming NMOS loads.
The source resistor R2 has one end connected to the source of the NMOS transistor N2. Three PMOS transistors P1, P2, P3 are scaled by a factor of one relative to one another to achieve a 1:1:1 scaling ratio. In addition, the three PMOS transistors have drains connected respectively to the three nodes 1, 2, 3 and gates commonly connected to the node 2, forming a PMOS current mirror.
Moreover, the resistor R3 and the diode D3 are connected in series between the node 3 and the ground, and a reference voltage is output through the node 3.
Subsequently, how the conventional reference voltage circuit operates will be explained. The conventional reference voltage circuit comprises a load circuit consisting of NMOS transistors (hereinafter, each referred to also as an NMOS load), resistors and a diode, and a PMOS current mirror circuit, in which both circuits are connected to each other via the two nodes 1, 2, to form a closed loop. In this case, the PMOS current mirror outputs bias currents scaled by a factor of one relative to each other to the NMOS loads. In the load circuit that has received the bias currents scaled by a factor of one relative to one another, the bias current passing through the source resistor R2 causes the gate-source voltage of the NMOS transistor N2 to become smaller.
The constant current Ic flowing through the NMOS transistor N2 is based on a gate-source voltage of the NMOS transistor N2, which voltage results from the fact that the same amount of current flows through the two NMOS transistors N1, N2, where the NMOS transistor N2 is scaled by a factor of m relative to the NMOS transistor N1. The constant current Ic is determined using the following formula (1) which is known to those skilled in the art.
Ic=(1/R2)*(kT/q)*ln(m)xe2x80x83xe2x80x83(1)
where (kT/q) is determined by the Boltzmann constant k in joules per degree Kelvin, the temperature T in degrees Kelvin (absolute scale) and the magnitude q of the charge of an electron, and is known as the thermal voltage, which is about 26 mV at a temperature of 300K.
The reference voltage Vref to be output from the conventional reference voltage circuit through the node 3 is the sum of the forward voltage, determined by the constant current Ic, of the diode D3 and the voltage across the resistor R3, and is determined using the following formula (2).
Vref=Vf+(R3/R2)*(kT/q)*ln(m)xe2x80x83xe2x80x83(2)
where the first term Vf on the right hand side of equation is the forward voltage of the diode D3 and has a negative temperature coefficient as is known to those skill in the art. When the source resistor R2 and the output resistor R3 are assumed to have the same temperature coefficient, the second term (R3/R2)*(kT/q)*ln(m) on the right hand side of equation is independent of the temperature coefficient of those resistors and has a positive temperature coefficient. Accordingly, when optimally designing the ratio between the magnitudes of the source resistor R2 and the output resistor R3, the temperature coefficients of the first and second terms serve to eliminate each other, allowing the reference voltage Vref to exhibit linear and approximately flat change with temperature.
FIG. 2 is a diagram illustrating how the reference voltage Vref changes with junction temperature Tj in the conventional reference voltage circuit. As shown in FIG. 2, the conventional reference voltage circuit outputs a reference voltage Vref different from a supply voltage and independent of temperature in a specific range of temperatures. The reference voltage circuit outputs a voltage determined with reference to a bandgap voltage reference and therefore, is referred to as a bandgap reference circuit.
Furthermore, when the ratio between the magnitudes of the source resistor R2 and the output resistor R3 is optimally designed, the conventional reference voltage circuit is able to output the reference voltage Vref that linearly changes with temperature in a specific range of temperatures. The gradient, changing with temperature, of the voltage Vref can optionally be determined so as to meet the characteristics of a subsequent circuit.
A CMOS semiconductor integrated circuit has been widely adopted for low power applications and in recent years, increasingly adopted for applications typified such as by an automobile and allowing usage over a wide range of temperatures. Furthermore, since a reference voltage circuit advantageously outputs a reference voltage Vref that exhibits constant and low dependence of voltage on temperature over a wide range of temperatures, the need for a family of products that incorporate therein a reference voltage circuit has been increasing.
However, in the conventional reference voltage circuit, when junction temperature Tj exceeds about 125. degree. C., the magnitude of leakage currents flowing through P-type diffusion layers and N-type diffusion layers within the circuit increases, becoming not negligible relative to the xe2x80x9cshould-bexe2x80x9d magnitude of the bias currents. This causes the ratio of currents flowing through the nodes 1, 2, 3 to be displaced from a 1:1:1 scaling ratio that represents the magnitude of the scaling performed on the W/L of the three PMOS transistors. Furthermore, this causes the aforementioned formulas related to the constant current Ic and the reference voltage Vref to be of no use. That is, as shown in FIG. 2, the dependence of the reference voltage Vref on temperature becomes non-linear, preventing the reference voltage circuit from expanding its availability over a wider range of temperatures.
Moreover, in order to address the above-described problem, for example, the technique disclosed in Japanese Patent Application No. 13(2001)-117654 provides a leakage current removal circuit connected in parallel to a node for outputting a voltage and disposed to remove leakage current from current flowing through the node. However, additionally providing a leakage current removal circuit to a reference voltage circuit increases the scale of the entire circuit and makes the circuit design for expanding circuit availability over a wider range of temperatures become complicated.
An object of the present invention is to provide a reference voltage circuit having ability to output a reference voltage that linearly changes with temperature over a wider range of temperatures and being usable over a still wider range of temperatures.
The reference voltage circuit of the invention includes: first, second, third MOS transistors being of one conduction type and having drains respectively connected to first, second, third nodes and gates commonly connected to the second node in order to constitute a current mirror circuit; first, second MOS transistors being of the other conduction type and having drains respectively connected to the first and second nodes and gates commonly connected to the first node in order to constitute a load circuit; a source resistor having one end connected to a source of the second MOS transistor of the other conduction type and constituting the load circuit; and an output resistor having one end connected to the third node used to output a reference voltage and constituting the load circuit, in which the reference voltage circuit is further constructed such that a dummy diffusion layer of the other conduction type is connected to at least the third node in order to set a ratio of currents leaking, during operation of the reference voltage circuit, through PN junctions of diffusion layers connected to the first, second, third nodes and being of the other conduction type equal to a ratio of currents leaking, during operation of the reference voltage circuit, through PN junctions of diffusion layers connected to the first, second, third nodes and being of one conduction type.
The above-described reference voltage circuit embodying various aspects of the invention can be described as follows.
That is, the reference voltage circuit according to the first aspect of the invention is constructed such that each of the ratios of currents leaking through PN junctions of diffusion layers is controlled by adjusting a ratio of peripheral lengths of PN junctions of corresponding diffusion layers connected to the first, second, third nodes. Alternatively, the reference voltage circuit is constructed such that each of the ratios of currents leaking through PN junctions of diffusion layers is controlled by adjusting a ratio of areas of PN junctions of corresponding diffusion layers connected to the first, second, third nodes.
The reference voltage circuit according to the second aspect of the invention is constructed such that the dummy diffusion layer of the other conduction type connected to at least the third node constitutes two dummy diffusion layers of two dummy MOS transistors being of the other conduction type and connected to the third and first nodes, and further, the two dummy MOS transistors do not allow bias current to flow therethrough. In this case, each of the peripheral lengths of PN junctions of corresponding diffusion layers is grouped into a channel portion facing a transistor and a non-channel portion other than the channel portion, and a ratio of a channel portion to a non-channel portion of each of diffusion layers being of the other conduction type and connected to the first, second, third nodes is equal to a ratio of a channel portion to a non-channel portion of each of diffusion layers being of one conduction type and connected to the first, second, third nodes.
The reference voltage circuit according to the third aspect of the invention is constructed such that the dummy diffusion layer of the other conduction type connected to at least the third node constitutes two dummy diffusion layers of the other conduction type connected to the third and first nodes and each of the two dummy diffusion layers does not allow bias current to flow therethrough.
The reference voltage circuit according to the fourth aspect of the invention is constructed such that the output resistor and the source resistor are formed as a polysilicon resistor, and the circuit further comprises a diode connected in series to the output resistor.
The reference voltage circuit according to the fifth aspect of the invention is constructed such that the first, second, third MOS transistors of one conduction type are configured to have channel widths scaled by a factor of one relative to one another.